Efficient Construction of Simultaneous Deterministic Finite Automata on Multicores Using Rabin Fingerprints

Abstract—The ubiquity of multicore architectures in modern computing devices requires the adaptation of algorithms to utilize parallel resources. String pattern matching based on finite automata (FAs) is a method that has gained widespread use across many areas in computer science. However, the structural properties of the pattern matching algorithm have hampered its parallelization. To overcome the dependencyconstraint between subsequent matching steps and exploit parallelism, simultaneous deterministic finite automata (SFAs) have been recently introduced. Given an FA A with n states, the corresponding SFA S(A) simulates n parallel instances of FA A. However, although an SFA facilitates parallel FA matching, SFA construction itself is limited by the exponential state-growth problem, which may result in O(n) SFA states for an FA of size n. The substantial space requirements incur proportional processing steps, both of which make sequential SFA construction intractable for all but the smallest problem sizes. In this paper, we propose several optimizations for the SFA construction algorithm, which greatly reduce the in-memory footprint and the processing steps required to construct an SFA. We introduce fingerprints as a spaceand time-efficient way to represent SFA states. To compute fingerprints, we apply the Barrett reduction algorithm and accelerate it using recent additions to the x86 instruction set architecture. We exploit fingerprints to introduce hashing for further optimizations. Our parallel SFA construction algorithm is nonblocking and utilizes instruction-level, data-level, and task-level parallelism of coarse-, mediumand fine-grained granularity. We adapt static workload distributions and align the SFA data-structures with the constraints of multicore memory hierarchies, to increase the locality of memory accesses and facilitate HW prefetching. We conduct experiments on the PROSITE protein database for FAs of up to 702 FA states to evaluate performance and effectiveness of our proposed optimizations. Evaluations have been conducted on a 4 CPU (64 cores) AMD Opteron 6378 system and a 2 CPU (28 cores, 2 hyperthreads per core) Intel Xeon E5-2697 v3 system. The observed speedups over the sequential baseline algorithm are up to 118541x on the AMD system and 2113968x on the Intel system.